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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTP10N10E/D Designer'sTM Data Sheet TMOS IV Power Field Effect Transistor This advanced "E" series of TMOS power MOSFETs is designed to withstand high energy in the avalanche and commutation modes. These new energy efficient devices also offer drain-to- source diodes with fast recovery times. Designed for low voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical, and offer additional safety margin against unexpected voltage transients. * Internal Source-to-Drain Diode Designed to Replace External Zener Transient Suppressor -- Absorbs High Energy in the Avalanche Mode -- Unclamped Inductive Switching (UIS) Energy Capability Specified at 100C * Commutating Safe Operating Area (CSOA) Specified for Use in Half and Full Bridge Circuits * Source-to-Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode * Diode is Characterized for Use in Bridge Circuits MTP10N10E TMOS POWER FETs 10 AMPERES 100 VOLTS RDS(on) = 0.25 OHM N-Channel Enhancement-Mode Silicon Gate (R) D G S CASE 221A-06, Style 5 TO-220AB MAXIMUM RATINGS (TC = 25C unless otherwise noted) Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 M) Gate-Source Voltage Drain Current -- Continuous Drain Current -- Pulsed Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Symbol VDSS VDGR VGS ID IDM PD TJ, Tstg Value 100 100 20 10 25 75 0.6 - 65 to 150 Unit Vdc Vdc Vdc Adc Watts W/C C THERMAL CHARACTERISTICS Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 seconds RJC RJA TL 1.67 62.5 275 C/W C Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design. Designer's is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. (c) Motorola TMOS Motorola, Inc. 1996 Power MOSFET Transistor Device Data 1 MTP10N10E ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0, ID = 0.25 mA) Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0) (VDS = 0.8 Rated VDSS, VGS = 0, TJ = 125C) Gate-Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) Gate-Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) ON CHARACTERISTICS* Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) TJ = 100C Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 5.0 Adc) Drain-Source On-Voltage (VGS = 10 V) (ID = 10 Adc) (ID = 5.0 Adc, TJ = 100C) Forward Transconductance (VDS = 15 V, ID = 5.0 A) DRAIN-TO-SOURCE AVALANCHE CHARACTERISTICS Unclamped Drain-to-Source Avalanche Energy See Figures 14 and 15 (ID = 25 A, VDD = 25 V, TC = 25C, Single Pulse, Non-repetitive) (ID = 10 A, VDD = 25 V, TC = 25C, P.W. 200 s, Duty Cycle 1%) (ID = 4.0 A, VDD = 25 V, TC = 100C, P.W. 200 s, Duty Cycle 1%) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS* (TJ = 100C) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge SOURCE-DRAIN DIODE CHARACTERISTICS* Forward On-Voltage Forward Turn-On Time Reverse Recovery Time INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) * Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%. Ld 3.5 (Typ) 4.5 (Typ) Ls 7.5 (Typ) -- -- -- nH (IS = Rated ID VGS = 0) VSD ton trr 1.4 (Typ) 1.7 Vdc (VDS = 0.8 Rated VDSS, ID = Rated ID, VGS = 10 V) See Figures 17 and 18 (VDD = 25 V, ID = 5.0 A, RG = 50 ) See Figure 9 td(on) tr td(off) tf Qg Qgs Qgd -- -- -- -- 15 (Typ) 8.0 (Typ) 7.0 (Typ) 50 80 100 80 30 -- -- nC ns (VDS = 25 V, VGS = 0, f = 1.0 MHz) See Figure 16 Ciss Coss Crss -- -- -- 600 400 100 pF WDSR -- -- -- 60 100 40 mJ VGS(th) 2.0 1.5 RDS(on) VDS(on) -- -- gFS 4.0 2.7 2.4 -- mhos -- 4.5 4.0 0.25 Ohm Vdc Vdc V(BR)DSS IDSS -- -- IGSSF IGSSR -- -- 10 80 100 100 nAdc nAdc 100 -- Vdc A Symbol Min Max Unit Limited by stray inductance 70 (Typ) -- ns 2 Motorola TMOS Power MOSFET Transistor Device Data MTP10N10E TYPICAL ELECTRICAL CHARACTERISTICS VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED) 20 16 VGS = 10 V 8V 7V TJ = 25C 1.2 VDS = VGS ID = 1 mA I D, DRAIN CURRENT (AMPS) 1.1 12 6V 1 8 5V 0.9 4 4V 0 8 12 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 4 20 0.8 0.7 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 150 Figure 1. On-Region Characteristics VBR(DSS), DRAIN-TO-SOURCE BREAKDOWN VOLTAGE (NORMALIZED) Figure 2. Gate-Threshold Voltage Variation With Temperature 20 TJ = -55C I D, DRAIN CURRENT (AMPS) 16 VDS = 10 V VDS = 15 V 12 100C 2 VGS = 0 V ID = 0.25 mA 1.6 1.2 8 +25C 0.8 4 0.4 0 0 4 6 8 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 2 10 0 -50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (C) Figure 3. Transfer Characteristics Figure 4. Breakdown Voltage Variation With Temperature RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) VGS = 10 V 0.4 TJ = 100C 25C -55C 0.1 RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 0.5 2 VGS = 10 V ID = 5 mA 1.6 0.3 1.2 0.2 0.8 0.4 0 2 4 6 8 10 0 -50 0 50 100 150 200 ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (C) Figure 5. On-Resistance versus Drain Current Figure 6. On-Resistance Variation With Temperature Motorola TMOS Power MOSFET Transistor Device Data 3 MTP10N10E SAFE OPERATING AREA INFORMATION 30 I D, DRAIN CURRENT (AMPS) 100 s 10 VGS = 20 V SINGLE PULSE TC = 25C 1 ms 10 ms dc 10 s I D, DRAIN CURRENT (AMPS) 40 TJ 150C 30 3 20 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 10 0.3 0 0 20 40 60 80 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 100 Figure 7. Maximum Rated Forward Biased Safe Operating Area FORWARD BIASED SAFE OPERATING AREA The FBSOA curves define the maximum drain-to-source voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. Because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. The curves are based on a case temperature of 25C and a maximum junction temperature of 150C. Limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. Motorola Application Note, AN569, "Transient Thermal Resistance-General Data and Its Use" provides detailed instructions. SWITCHING SAFE OPERATING AREA The switching safe operating area (SOA) of Figure 8 is the boundary that the load line may traverse without incurring damage to the MOSFET. The fundamental limits are the peak current, IDM and the breakdown voltage, V(BR)DSS. The switching SOA shown in Figure 8 is applicable for both turn- on and turn-off of the devices for switching times less than one microsecond. 1 0.7 0.5 0.3 0.2 0.1 0.1 0.07 0.05 0.03 0.02 SINGLE PULSE 0.01 0.01 0.02 0.03 0.05 0.05 0.01 P(pk) Figure 8. Maximum Rated Switching Safe Operating Area The power averaged over a complete switching cycle must be less than: TJ(max) - TC RJC 1K 500 300 200 t, TIME (ns) 100 70 50 30 20 10 7 5 3 2 1 1 23 5 10 20 30 50 100 200 300 500 RG, GATE RESISTANCE (OHMS) 1K VDD = 25 V ID = 5 A VGS = 10 V TJ = 25C td(off) tf tr td(on) Figure 9. Resistive Switching Time versus Gate Resistance r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED) D = 0.5 0.2 t2 DUTY CYCLE, D = t1/t2 0.1 0.2 0.3 0.5 1 23 5 t, TIME (ms) 10 20 30 t1 RJC(t) = r(t) RJC RJC = 1.67C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 50 100 200 300 500 1000 Figure 10. Thermal Response 4 Motorola TMOS Power MOSFET Transistor Device Data MTP10N10E COMMUTATING SAFE OPERATING AREA (CSOA) The Commutating Safe Operating Area (CSOA) of Figure 12 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. The curve shows the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure 11 are present. Full or halfbridge PWM DC motor controllers are common applications requiring CSOA data. Device stresses increase with increasing rate of change of source current so dIs/dt is specified with a maximum value. Higher values of dIs/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking. VDS(pk) is the peak drain-to-source voltage that the device must sustain during commutation; IFM is the maximum forward source-drain diode current just prior to the onset of commutation. VR is specified at 80% of V(BR)DSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero. RGS should be minimized during commutation. TJ has only a second order effect on CSOA. Stray inductances in Motorola's test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dIs/dt of 400 A/s. 30 + IS , SOURCE CURRENT (AMPS) 25 20 15 dIs/dt 400 A/s 10 5 0 15 V VGS 0 IFM 90% IS 10% ton IRM 0.25 IRM VDS(pk) VR VDS dVDS/dt VdsL MAX. CSOA STRESS AREA dls/dt trr Vf Figure 11. Commutating Waveforms RGS DUT - VR IFM + 20 V - IS VDS Li VGS VR = 80% OF RATED VDS VdsL = Vf + Li dls/dt Figure 13. Commutating Safe Operating Area Test Circuit 0 100 20 40 60 80 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 120 V(BR)DSS Vds(t) IO L VDS ID C 4700 F 250 V VDD t RGS 50 VDD tP WDSR t, (TIME) ID(t) Figure 12. Commutating Safe Operating Area (CSOA) + 1 LI 2 O 2 V(BR)DSS V(BR)DSS - VDD Figure 14. Unclamped Inductive Switching Test Circuit Motorola TMOS Power MOSFET Transistor Device Data Figure 15. Unclamped Inductive Switching Waveforms 5 MTP10N10E Ciss 1000 C, CAPACITANCE (pF) Coss 750 TJ = 25C VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1250 10 8 VDS = 30 V 50 V 6 80 V TJ = 25C 500 Ciss Coss Crss 4 ID = RATED ID 2 250 0 20 10 0 10 20 30 0 0 4 VGS VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) 8 12 QG, TOTAL GATE CHARGE (nC) 16 20 Figure 16. Capacitance Variation Figure 17. Gate Charge versus Gate-To-Source Voltage +18 V VDD 1 mA 47 k Vin 15 V 2N3904 2N3904 100 k 47 k 100 FERRITE BEAD 10 V 100 k 0.1 F SAME DEVICE TYPE AS DUT DUT Vin = 15 Vpk; PULSE WIDTH 100 s, DUTY CYCLE 10% Figure 18. Gate Charge Test Circuit 6 Motorola TMOS Power MOSFET Transistor Device Data MTP10N10E PACKAGE DIMENSIONS -T- B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 --- --- 0.080 MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 --- --- 2.04 Q 123 A U K STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN H Z L V G D N R J CASE 221A-06 ISSUE Y Motorola TMOS Power MOSFET Transistor Device Data 7 MTP10N10E Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 8 Motorola TMOS Power MOSFET Transistor Device Data MTP10N10E/D *MTP10N10E/D* |
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